Sri Lanka leads at Manthan Award South Asia 2010

 Sri Lanka topped the region by winning six awards out of 57 projects nominated by the ICT Agency of Sri Lanka (ICTA) at the Manthan Award South Asia 2010 held in New Delhi recently. 

 The 10.5 to hundred ‘awards to nominations’ ratio, puts Sri Lanka ahead of all the other  seven participating countries. Bangladesh came a close second to Sri Lanka with a 9. 8 % awards to nominations ratio on the basis of the five awards it won out of 51 nominations while India’s 28 awards came from 313 nominations  - 8.95 per cent ratio.  The overall ratio yielding 41 awards out of a  post-screening total of 434nominations stands at 9.4 %. 

This year eight countries – Afghanistan, Bangladesh, Bhutan, India, Maldives, Nepal, Pakistan and Sri Lanka participated  under 15 categories resulting in  41 winning projects. With the addition of the two new categories ‘e-Agriculture’ and ‘e-Travel and Tourism’ in the 2010 list of categories , applications submitted were considered under – ‘e-Agriculture and Livelihood’, ‘e-Business and Enterprise’, ‘e-Culture and Heritage’, ‘e-Education’, ‘e-Entertainment’, ‘e-Environment’, ‘e-Government’, ‘e-Health’, ‘e-Inclusion’, ‘e-Learning’, ‘e-Localisation’, ‘e-News and Media’, ‘e-Science’, ‘e-Travel and Tourism’ and ‘Community Broadcasting’. 

The Manthan Award  organised by the Digital Empowerment Foundation and centred in New Delhi, India, aims to bring to the fore projects  in e-content and promote best practices and creativity in e-content. The two-day session of the seventh edition of the Manthan Award for presentation of projects culminated  with Awards Gala held on December 17 and 18th at Parkland Exotica Hotel Delhi.  

The Foundation has been guided by its founder Chairman Osama Manzar since  inception in December 2002 and selection of award winning projects is carried out by an international jury comprising relevant specialists under a stringent selection procedure. This year the international jury consisted of 22  professionals including ICTA e-Society Project Manager Indumini Kodikara who spent long hours in meticulous consideration of the nominated projects. 

ICTA prepares the ICT enthusiasts of the island for both regional awards like the Manthan Award and the international awards like the World Summit Award. This preparation by ICTA was articulated  by its e-Swabhimani programme. ICTA  nominated respectively 42 and 57 best  e-Content projects submitted for e-Swabhimani 2009  and 2010  for Manthan Award 2009 and 2010.

Referring to the awards and in particular the progressive achievements in making the mark at the regional event, ICTA CEO Reshan Dewapura said that being awarded five  and six awards at Manthan Awards South Asia 2009 and 2010  respectively confirmed that Sri Lanka was making  steady progress in the ICTA sector. “Regional and international awards like Manthan and World Summit Awards for participation in which  ICTA’s e-Swabhimani  plays an important role, give great impetus for e-Content development in Sri Lanka. These projects on their part greatly assist in putting into effect His Excellency President Mahinda Rajapaksa’s goal of making the lives of all people, in particular the differently abled, distanced, rural and otherwise disadvantaged, as comfortable as possible by the use of ICT”, ICTA CEO added. 

 

The projects that won awards at Manthan Awards South Asia 2010 and short description about them according to the producers are as follows:

 

1. Aba, a 3D game produced by Game Core under the  category of e-Cutlure and Entertainment centres on a series of events that took place about 2400 years ago in the Panduvasadeva Palace of Upatissa Nuwara. Set in 400 BC the player in the game is Prince Pandukabhaya and the weapons he uses are those which were used in the era concerned. (www.gameslk.com)

 

2. SALA Pro Sat GPS Navigator submitted by producer Sala Gis Pvt. Ltd. under the  category of ‘e-Localisation’will guide  travelers and help them to find any location  in Sri Lanka such as hotels, ATMs, fuel stations and  places of historical interest . The voice guidance is available in many languages including Sinhala, English, Russian and German. It is noteworthy that it is developed according to the Sri Lankan traffic laws. (www.salagis.com)

 

3. Ceylonmap.com. produced by Marius Sanjeeva Jayasuriya  under the category ‘e-Localisation’ and available in Sinhala, Tamil and English aims at providing an easy way for locating places and tourist attractions. Just by rolling the mouse over the required part of the map the users can immediately obtain information about the area concerned by way of text, links and illustrations. (www.ceylonmap.com)

 

4. SiyaBasScript, produced by Keheliya Bandara Gallaba coming under category e-Localisation, is a Mozilla Firebox and Google Chrome extension

LOGIC GATES

Navigation

2.1 NAND gate ICs	More updated pages...
2.2 NAND gate truth table
2.3 Other gates using NAND gates	555 timer
2.4 Building an EXOR gate	4060 counter/divider
2.5 More logic ICs
2.6 Schmitt trigger logic gates	Safety Lights Project
2.7 What have you learned?
2.8 Bookshelf
Chapter 1: BEGINNINGS
Chapter 3: ASTABLES

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2.1 NAND gate ICs

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Now that you can produce HIGH and LOW logic signals and monitor the logic state of any point in a circuit, either by connecting a voltmeter, or by lighting up an LED, you can start to investigate the properties of logic gates and other logic integrated circuits.
NAND gates are the most useful variety of logic gate because they can be connected together to make all the other types of gate, including AND, OR, NOR and EXOR. In fact, many logic integrated circuits have an internal structure which consists entirely of NAND gates. Different gates have different symbols described later in this Chapter.
There are several families of logic ICs, each with particular properties and power supply requirements. One of the most important distinctions is between 74 series devices which are intended for use with a 5 V power supply, and 4000 series devices, which can work with any power supply from 3-15 V. It is essential to know that the pin arrangements of the two types of IC are quite different. You can't replace a 74 series NAND gate IC by plugging a 4000 series device into the same socket.
The diagrams below show the pin layout for NAND gate ICs in each of the two series:

Pin layouts of NAND gate ICs

The first 74 series devices were manufactured using a technology known as transistor-transistor logic, or TTL. The first 4000 series devices used an alternative technology known as complementary metal oxide silicon, or CMOS.
The technology of manufacturing integrated circuits does not stand still. More recent versions of 74 series devices remain compatible with the original devices in the sense that they have the same power supply requirements, can be used in the same circuits, and have identical pin arrangements. However, the TTL manufacturing process is largely obsolete and most new 74 series devices are made using developments of the CMOS process.
It is not necessary for you to know the details of all the different logic families at this point in the course, provided you remember that a 74 type number IC is going to need a 5 V power supply, while a 4000 type number IC can operate with power supplies from 3-15 V. In general, 4000 series devices require less current and are useful for battery-operated projects.

 

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2.2 NAND gate truth table

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Build the circuit shown in the diagram below. You can do this from scratch, or by inserting a 4011 CMOS IC and rearranging some of the components on the prototype board saved from Chapter 1.

4011: NAND gate truth table

Clicking the new button under the diagram opens a small window showing the pin layout for the 4011, so that you can check the inputs and outputs of the individual NAND gates.
With CMOS circuits, it is good practice to include a decoupling capacitor, 47 μF, or 100 μF, connected across the power supply. This prevents the transmission of voltage 'spikes' along the power supply lines. More complex circuits won't function properly without decoupling capacitors and you should think of them as part of the recipe needed to get CMOS circuits to work.
The push button switches are wired with pull down resistors. What kind of logic signal will you get when you press the button? With pull down resistors, you get a HIGH voltage, logic 1, when the switch is pressed. Operate the switches in all combinations to complete the following table:

switch B	switch A	output
open	open	LOW, logic 0 HIGH, logic 1
open	closed	LOW, logic 0 HIGH, logic 1
closed	open	LOW, logic 0 HIGH, logic 1
closed	open	LOW, logic 0 HIGH, logic 1

 The output is HIGH when the LED is illuminated and LOW when the LED is off. Representing an open switch by '0' and a closed switch by '1' and writing '0' for LOW and '1' for HIGH should give the NAND gate truth table:

input B	input A	output
0	0	1
0	1	1
1	0	1
1	1	0

NAND gate truth table

Check through your circuit until you get this result. Possible errors include misplaced, or missing wire links.
By convention, input A is the rightmost input column. The reason for this becomes clear when you find out more about binary numbers: A refers to the least significant bit of a binary number.
Now modify your circuit, as shown in the next prototype board layout:

4011: Driving LEDs using NAND gates

This gives you two new ways of driving an LED. The circuit diagram for the system you have built is:

Driving LEDs using NAND gates: circuit diagram

The small numbers correspond to the pins of the 4011 IC.
Although LED 1 and LED 2 are both connected to a NAND gate with its inputs connected together, they are driven in different ways. LED 1 is connected between +4.5 V and the output of the second NAND gate, pin 11. This means that LED 1 will light up when the output of the driving NAND gate goes LOW. Check that LED 1 follows the NAND gate truth table, as before.
Now compare this with the behaviour of LED 2, wired from the output of the third NAND gate, pin 4, to 0 V. LED 2 lights up when the output of its NAND gate goes HIGH. As a result, its behaviour is opposite to that of LED 1. In fact, LED 2 follows the AND gate truth table, as follows:

input B	input A	output
0	0	0
0	1	0
1	0	0
1	1	1

AND gate truth table

In this circuit, you have used NAND gates connected to make two other gates. These are NOT and AND gates:

NOT and AND gates

Looking again at the circuit diagram, you can see that the output of the first NAND gate is a valid logic signal. The current taken from this point by the other two NAND gates is small and what is meant to be a HIGH voltage will actually be a HIGH voltage. This is not true after the NAND gates which drive the LEDs. 4011 NAND gates can provide just enough current to drive LEDs, but the HIGH and LOW voltages will be pulled away from their normal values and must not be used as inputs to other parts of the logic circuit.
It is instructive to measure the HIGH and LOW voltages at the outputs of the gates using a voltmeter (you know how to do this) and compare these values with the normal HIGH and LOW voltages.

• You can use a logic gate to substitute for a transistor in driving an LED provided you remember that the output of the logic gate is no longer a valid logic signal.

 

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2.3 Other gates using NAND gates

Start again with the prototype board layout used for investigating the NAND gate truth table:

NAND gate truth table

Modify the circuit by rearranging links. The new links are shown in yellow:

Which logic gate is this?

Confirm that this circuit follows the truth table of an AND gate. It will if you inserted the new links correctly. Rearrange the links again:

Which logic gate is this?

A little care is needed to locate the links correctly. Zoom in to check. Open the popup window showing the pin diagram of the 4011. (If nothing appears, you may already have opened this window and will be able to select it from the task bar.) Can you work out how the NAND gates are connected?
The circuit diagram looks like this:

Connecting NAND gates to make an OR gate

You should find that the circuit follows the truth table for an OR gate:

input B	input A	output
0	0	0
0	1	1
1	0	1
1	1	1

OR gate truth table

How can you make a NOR gate? This is easy: add a NOT gate to the existing circuit:

Building a NOR gate from NAND gates

Confirm that your circuit follows the truth table for a NOR gate:

input B	input A	output
0	0	1
0	1	0
1	0	0
1	1	0

NOR gate truth table

If you have built and tested all these circuits on prototype board, you will have started to see how versatile NAND gates can be. Soon you won't be able to forget how the individual NAND gates are arranged inside the 4011. This is good because lots of other 4000 series logic ICs with different gates share the same arrangement.

 

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2.4 Building an EXOR gate

To work out an arrangement of NAND gates which will give the same truth table as exclusive OR, also called EXOR, XOR and EOR, requires a little more thought. The truth table for EXOR is:

input B	input A	output
0	0	0
0	1	1
1	0	1
1	1	0

EXOR gate truth table

How does the truth table differ from the ordinary version of an OR gate, also known as inclusive OR? Check back if you don't know.
To work out the NAND gate circuit, you need to summarise the truth table in a different way. Look at the output column. The output is 1 when:

• A is 1 AND B is 0 (NOT B)
• OR when
• A is 0 (NOT A) AND B is 1

These slightly strange statements give a clue as to how the circuit must be built. Each of the parts of the statement can be replaced by the appropriate logic gate, AND, OR, or NOT:

EXOR using NOT, AND, and OR

The diagram uses the symbols for NOT, AND and OR gates. Identify input A. The output of the first NOT gate is the opposite of A, or NOT A, often written as . You should be able to see that the output of the top AND gate will be 1 when (A is 0 AND B is 1). Similarly, the output of the second AND gate will be 1 when (A is 1 AND B is 0).
Placing an OR between these statements means that the final output is 1 if (A is 0 AND B is 1) OR (A is 1 AND B is 0), matching the EXOR truth table.
The next step is to replace the NOT, AND and OR gates with their NAND gate equivalents:

Substituting NAND gate equivalents

This circuit uses only NAND gates, but can be simplified by removing double NOT gates, as follows:

Removing double NOT gates

The process described above for working out the NAND gate equivalent which gives the EXOR truth table can be used to solve any simple logic problem. The steps in the process are:

1. Work out the truth table for the logic system.
2. Use the output column of the truth table to work out a logic statement which describes the action of the logic system. This involves writing a statement for each line in the truth table for which the output is 1, and linking these statements with OR.
3. Convert the logic statement into a network of gates using AND, OR, NOT, as appropriate.
4. Replace AND, OR, NOT by their NAND gate equivalents.
5. Simplify the circuit by removing any double NOT gates.

This is quite close to the methods of Boolean Algebra, described later in Discovering Digital Electronics.
You could verify the NAND gate circuit for EXOR by building it on prototype board, but don't unless you are seriously keen.

 

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2.5 More logic ICs

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The 4000 series includes NOT gate ICs, and ICs with 2-input AND, OR, NOR and EXOR gates. In addition, 3-input, 4-input and 8-input gates are available. The Beastie Zone lists the most useful devices.
As an example, here is the test circuit for a 4002 4-input NOR gate:

Test circuit for 4002 4-input NOR gate

This circuit uses a 9 V power supply. When you build the prototype board version, connect a 9 V PP3 battery instead of the 3xAA 4.5 V arrangement you have been using so far. You can use the same battery clip:

 

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4002: Test circuit for 4-input NOR gate

Click the pins symbol to see how the gates are arranged inside the integrated circuit.
You have already seen the truth table for a 2-input NOR gate:

input B	input A	output
0	0	1
0	1	0
1	0	0
1	1	0

NOR gate truth table

What do you think the truth table for a 4-input NOR gate will be?
Because there are 4 inputs, the truth table will have 2⁴=16 lines:

input D	input C	input B	input A	output
0	0	0	0	1
0	0	0	1	0
0	0	1	0	0
0	0	1	1	0
0	1	0	0	0
0	1	0	1	0
0	1	1	0	0
0	1	1	1	0
1	0	0	0	0
1	0	0	1	0
1	0	1	0	0
1	0	1	1	0
1	1	0	0	0
1	1	0	1	0
1	1	1	0	0
1	1	1	1	0

4-input NOR gate truth table

As you can see, the output is '1' only when all four inputs are '0', that is, when none of the four input switches are pressed. Shading is intended to make the table easier to follow.
Check the truth tables of other 3-input and 4-input gates from the Beastie Zone. How many lines would there be in the truth table for an 8-input logic gate?

 

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2.6 Schmitt trigger logic gates

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Typical CMOS inputs have a single threshold. If the voltage applied to the input is less than half the power supply voltage, it counts as a '0', while if the voltage is more than half the power supply voltage, it counts as a '1'.
A Schmitt trigger input has two different thresholds. The best way of understanding how this works is to investigate the behaviour of a Schmitt trigger device in a practical circuit. The circuit below uses a 40106 hex inverting Schmitt trigger (NOT gate):

40106: Investigating a Schmitt trigger NOT gate

Build the circuit and then adjust the 10 kΩ potentiometer until the voltmeter reads close to 0 V. The input to the NOT gate clearly counts as a '0'. Click the pins button to see how the gates are arranged inside the 40106.
Since the input to the NOT gate is '0', the output is '1' and the indicator LED is illuminated.

 

Now slowly adjust the potentiometer to increase the input voltage. Note the voltage reached when the LED suddenly switches off. This is the first threshold. Carry on increasing the voltage up to 9 V.
Adjust the potentiometer slowly in the opposite direction, decreasing the voltage at the input to the NOT gate. What happens when the voltage reaches the first threshold? Nothing happens: the LED remains off. Keep on reducing the input voltage and note the voltage reached when the LED suddenly switches on. This is the second threshold.
Repeat the experiment several times: the device has two distinct thresholds depending on whether you start adjusting the voltage from 0 V, or from 9 V. A device like this is said to show hysteresis. Typically, these thresholds are located at 1/3 and 2/3 of the power supply voltage, 3 V and 6 V with a 9 V power supply.
Plotting a graph of output voltage against input voltage gives the result shown in the next diagram:

Graph showing the action of a Schmitt trigger NOT gate

Click the button to start the animation and note the result as the input voltage is first increased, then decreased.
Why would you want a Schmitt trigger logic gate?
A gate with a single switching threshold behaves erratically if the input signal is noisy or degraded. If the input voltage is close to the threshold, the output is likely to oscillate between 0 and 1, or may be somewhere in between. With a Schmitt trigger gate, this is impossible. The output is either 0 or 1 and cannot be intermediate. Schmitt trigger devices are often used to 'clean up' noisy input signals, passing on a tidy sequence of 0's and 1's to other parts of the circuit. This is what Schmitt trigger devices are for.
A useful bonus of Schmitt trigger behaviour is that you can make an astable using one resistor, one capacitor and a Schmitt trigger NOT gate. Modify your prototype board as follows:

40106: Schmitt trigger NOT gate astable

The circuit diagram for this system looks like this:

Schmitt trigger NOT gate astable

You might notice that the LED is illuminated for longer when power is first applied. To understand why click to draw the graph:

Graph showing Schmitt trigger astable input and output voltages

Initially, the capacitor is empty and must charge from 0 to 6 V to reach the first Schmitt trigger threshold. When this is reached, the output of the NOT gate snaps LOW and the capacitor starts to discharge. When the second threshold is reached, 3 V with a 9 V power supply, the output of the NOT gate snaps HIGH once more. This time, the capacitor is already partly charged and the duration of the second pulse corresponds with the time take to charge from 3 V to 6 V.
The HIGH and LOW times of the astable pulse output each correspond to a half charge time, 0.69RC. The period of the pulse waveform is 0.69RC + 0.69RC and the frequency of the pulses is given by:

In practice, the Schmitt trigger thresholds are not fixed exactly and it is better to approximate the frequency as:

This is a great way of making a cheap and cheerful astable for testing a counter circuit, but is not the astable to choose if you want an exact frequency.